Partial Reconfiguration in the Field of Logic Controllers Design

The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process

Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA

In the paper an implementation of algorithm of Petri net array-based synthesis is presented. The method is based on decomposition of colored interpreted macro Petri net into subnets. The structured encoding of places in subnets is done of using minimal numbers of bits. Microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. This algorithm is implemented in C# and delivered as a stand alone library

Transition based synthesis with modular encoding of Petri nets into FPGAs

The paper describes a new method for the synthesis of the application specific logic controllers, targeted into the FPGA. The initial steps of the proposed control algorithm rely on the notion of a Petri net, which is an easy way to describe parallel processes. The algorithm is oriented on transition based logic description. It allows easy analysis of dynamics and functioning of the circuit. The logic circuit is also decomposed into logic blocks responsible for particular functions. It leads to the compact implementation with usage of different kind of logic elements like. Additionally such decomposition allows easy analysis of circuit

SYNTHESIS OF FINITE STATE MACHINES FOR PROGRAMMABLE DEVICES BASED ON MULTI-LEVEL IMPLEMENTATION

promotor: prof. dr hab. inż. Alexander Barkalov

DATICS-2010: Welcome message from workshop organizers: FutureTech 2010

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Preface of the 2010 IAENG International Conference on Electrical Engineering special session: Design, analysis and tools for integrated circuits and systems

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